Albin Engineering Services, Inc. – FPGA Design Verification Engineer

Albin Engineering Services, Inc. (AESI) is seeking an experienced FPGA Design Verification Engineer to work on a 6 month contract for a leading Aerospace company in San Jose, CA.

Requirements:

• Must be fluent in both Verilog and VHDL, and both RTL (synthesizable) and behaviora System Verilog is a plus
• Capable of writing scripts (e.g. PERL, TCL, C) that will batch numerous simulation jobs and alter/skew parameters to verify worst case conditions
• Knowledge of Xilinx Virtex 2 Pro and Virtex 4 a plus
• Experience using Modelsim SE, Precision Synthesis, Xilinx ISE a plus
• Capable of modeling systems in Matlab, Simulink, C are a plus
• Must be US Citizen

Please send your resume to David Fletcher or call 408-733-2374 x 30.